Motion Estimation Algorithm for HEVC Suitable for Hardware Implementation

HEVC being developed in the video coding standard(The video coding standard of HEVC being developped ) is a new generation of video coding standards for HD resolution video encoding. It is difficult to implement HEVC real time coding in current hardware for the algorithm’s complextivity, so the algorithm optimization and hardware acceleration of HEVC become research hot spots. The motion estimation unit of HEVC occupy more than 50% of the computation time in the ITU-T standard coding software, so the algorithm optimization can reduce the encoding time largely. Therefore,this paper proposes a new parallel processing method that the LCU and the PU block are divided for computing motion estimation parameters at the same time. The test results shows that, PSNR is decreased 0.005db and compression rate is decreased 0.026 percentage , the algorithm can increase the processing speed of motion estimation by 77.2%, compare with full search algorithm. The paper algorithm is suitable for hardware implementation, for the parameters of various motion estimation block in the same LCU can be computed parallelly and memery access is regular. Key-Words: Video Coding, HEVC/H.264 encoder, Fast Motion Estimation, 1080P, Parallel Computing